The invention relates to a method of forming a configuration of interconnections on a semiconductor device, more particularly an integrated circuit, this method comprising the following steps:
(a) forming an insulating layer on the substrate, in which the elements of the device are provided, PA1 (b) etching narrow contact openings into this insulating layer, PA1 (c) depositing at least one layer of conductive material by means of a method ensuring a good coverage, inclusive of the inner surface of the contact openings, the overall thickness of said layer being sufficient to fill the volume of the contact openings, PA1 (d) removing by etching the major part of the conductive material to expose the surface of the insulating layer, but to maintain the material in the contact openings, PA1 (e) depositing a metallic interconnection layer and etching it into the form of the desired configuration. PA1 (a) forming an insulating layer on substrate, on which the elements of the device are provided, PA1 (b) etching narrow contact openings into this insulating layer, PA1 (c) depositing at least one layer of conductive material by means of a method ensuring a good coverage inclusive of the inner surface of the contact openings, the overall thickness of this layer being sufficient to fill the volume of the contact openings, PA1 (d) removing by etching the major part of the conductive material to expose the surface of the insulating layer, but to maintain material in the contact openings, PA1 (e) depositing a metallic interconnection layer and etching it into the form of the desired configuration,
The semiconductor technology shows a constant development towards an increasingly higher integration of the number of elementary parts in the same monolithic circuit.
For this purpose and in order to increase the speed of operation of the circuits, there is a tendency to reduce as far as possible the dimensions of the elementary parts. The conventional techniques of forming contacts on the semiconductor devices used until recently contact zones and interconnection lines whose lateral dimensions most frequently were considerably larger than the thickness of the metallic layer constituting the said lines. As far as the manufacture of circuits having a high integration density is concerned, it is on the contrary necessary to provide contact openings whose diameter is of the same order as the thickness of the insulating layer, in which these contact openings are formed. In this connection, reference is frequently made to the ratio between the depth and the diameter of the contact openings designated as "aspect ratio", which, when this ratio is close to 1 or even larger, indicates that the known techniques of forming contacts based especially on the simple deposition of an aluminum layer can no longer be used successfully.
Thus, the method mentioned in the opening paragraph has been proposed to provide a solution suitable for the formation of a configuration of interconnections on a circuit having a high integration density, in which the contact openings have an aspect ratio close to or larger than 1.
A method of this kind is known from the document EP-A-0 165 185. Among the conductive materials intended for filling the contact openings, titanium and tungsten are mentioned. It is otherwise known that a particularly interesting solution from the viewpoint of performances: especially a low electrical resistance and a good mechanical behaviour, consists in that first a thin layer of titanium-tungsten alloy is used as adhesion and covering layer for the whole surface and then a thick layer of tungsten is formed for effectively filling the contact openings.
The method generally used for depositing the tungsten layer for filling the contact openings is that designated as low-pressure chemical vapour deposition (LPCVD) method.
In fact this method ensures a good coverage of the whole surface from the layer of Ti-W alloy serving to activate the nucleation of deposition of tungsten. The filling of the contact openings is obtained when the thickness of the deposited layer is at least equal to half the diameter of these openings.
According to this method, after etching the layer of tungsten in such a manner that only the parts of this layer contained within the contact openings are maintained, it is observed that the upper surface of the insulating layer thus exposed frequently has a more or less pronounced roughness which can be irregularly disturbed over the substrate.
This degradation of the flatness of the surface of the insulating layer seems to be associated with the formation of micro-crystals in the layer of conductive material serving for filling the contact openings. In fact, this layer is necessarily fairly thick and is therefore obtained in conditions which promote a comparative high rate of deposition in such a manner that the method remains economical.
During the step of etching the conductive material, it is common practice that the etch employed is not selective with respect to the material of the insulating layer and that there is therefore a tendency to attack a superficial fraction of said insulating layer in order to guarantee the complete elimination of the conductive material everywhere except in the contact openings.
The surface roughness is then associated with the insulating layer.
The continuation of the manufacturing process of the semiconductor device is seriously disturbed by the appearance of this fault. In fact, the surface roughness of the insulating layer influences the crystallization of the metallic interconnection layer generally made of aluminum, which subsequently covers it and result in a reduction of the resistance to electromigration of this metallic layer.
On the other hand, the roughness is also reproduced at the surface of the metallic layer and during the operation of photomaking this layer leads to a substantial degradation of the optical definition of the masque of lacquer to be formed for locally etching the metallic layer.